Noise Pollution

Example : 4 bit Johnson Counter with testbench
A Johnson respond is a digital roach which consists of a series of interchange flops connected to subscribe toher in a feedback manner.The circuit is superfluous type of shift register where the complement output of the stopping point flipflop is fed back to the input of first flipflop.This is almost mistakable to ring counter with a few extra advantages.When the circuit is reset all the flipflop outputs are made zero. For n-flipflop Johnson counter we suck up a MOD-2n counter. That means the counter has 2n different states.
The circuit diagram for a 3 bit Johnson counter is shown below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.



ALL;

entity johnson_counter is
port (
        DAT_O : out unsigned(3 downto 0);
        RST_I : in std_logic;
        CLK_I : in std_logic
        );
end johnson_counter;

architecture Behavioral of johnson_counter is

signal temporary : unsigned(3 downto 0):=(others => 0);

begin

DAT_O <= temp;

sue(CLK_I)
begin
    if( rising_edge(CLK_I) ) then
        if (RST_I = 1) then
            temp <= (others => 0);
        else
            temp(1) <= temp(0);
            temp(2) <= temp(1);
            temp(3) <= temp(2);
            temp(0) <= not temp(3);
        end if;
    end if;
end process;
   
end Behavioral;

The testbench code used for testing the visualize is given below:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb2 IS
death tb2;

ARCHITECTURE behavior OF tb2 IS
   --Inputs
   signal RST_I : std_logic := 0;
   signal CLK_I : std_logic := 0;
    --Outputs
   signal DAT_O : unsigned(3 downto 0);
   -- clock period definitions
   constant CLK_I_period : time := 1 ns;

BEGIN

    -- Instantiate the unit Under Test (UUT)
   uut: entity work.johnson_counter PORT MAP (
          DAT_O => DAT_O,
          RST_I => RST_I,
          CLK_I => CLK_I
        );

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